This invention relates to a semiconductor integrated circuit having a double-gate MOS field-effect transistor (MOSFET) and a method for manufacturing the same, and more particularly to a semiconductor integrated circuit having double-gate MOSFETs each with an upstanding channel region laterally formed and a method for manufacturing the same.
When miniaturization for realizing the high-integration and high-speed of the MOSFET is advanced, a source and drain approach each other so that a drain electric field affects the source, thereby deteriorating the device characteristic. This is generally called “short channel effect”. This effect includes reduction in the threshold, slow-down of the rise of a drain current to a gate voltage (increase of S-factor), increase in the leak current between the source and drain, etc. On the other hand, as well known, a double-gate MOS gate structure in which a thin channel region is sandwiched between two gates can effectively shield the drain electric field, thereby suppressing the short-channel effect. Therefore, it has been considered that the double-gate MOSFET is suitable to a transistor structure most suitable to miniaturization.
There are three kinds of the double-gate MOSFET, inclusive of a planar type in which a thin channel layer is sandwiched by upper and lower two gates; an upstanding thin film lateral channel type in which an upstanding channel layer is sandwiched by two gates from the left and right sides to pass a current laterally (because the shape resembles a fin, it is often called a fin type; in this specification also, hereinafter referred to as the fin type); an upstanding thin film vertical channel type in which the upstanding thin channel layer is sandwiched between the two gates from the left and right sides to pass a current vertically. In recent years, the research and development of the fin type double-gate FET, because its manufacturing process is simple, has been actively advanced. Meanwhile, since the fin type MOSFET is generally formed on an SOI (Silicon-On-Insulator) substrate, the height of a silicon fin (Si-fin) serving as a channel (hereinafter also referred to as a silicon fin channel) is the same as the thickness of the silicon layer of the SOI substrate. Thus, the height of the fin channel is identical for all the transistors formed on the same substrate. In the fin type MOFET, although the value twice as large as the height of the silicon fin channel corresponds to an effective channel width, in order to increase an ON current, it is necessary to form a multi-fin channel (for example, see non-Patent Reference 1). In addition, in an actual integrated circuit, in order to constitute a CMOS inverter, since the mobility of holes is less than half of that of electrons, in consideration of balance of the current, the channel width of a p-channel MOSFET (pMOS) must be designed to be wider than those of an n-channel MOSFET (for example, see non-Patent Reference 2). Thus, where the CMOS inverter is formed by the fin type MOSFETs, the number of the fin channels of the pMOS will be made larger than that of the nMOS.
FIG. 14A is a plan view of a conventional CMOS integrated circuit formed using an SOI substrate. FIG. 14B is a sectional view taken in line A-A′ in FIG. 14B. In FIG. 14, reference numeral 1 denotes a silicon substrate; 2 an embedded oxide film; 3p, 3n a gate electrode; 4 an insulating film; 5p, 5n a channel region; 6 a gate insulating film; 7p, 7n a source region; and 8p, 8n a drain region (subscript “p” represents pMOS, and subscript “n” represents nMOS). Like this, since it is necessary to realize large-current driving by increasing the number of the silicon fin channels, the device design and manufacturing process become complicate. Further, if the number of the silicon fin channels is increased, the area of the multi-fin MOSFET correspondingly increases, thus leading to a disadvantage of reduction in the degree of integration.
Further, in the double-gate MOSFET which shows its feature when the thin channel layer is miniaturized, as a technique of controlling the threshold voltage indispensable to the CMOS circuit, impurity control in the channel region which has been usually adopted is not effective. This is because in the miniaturized double-gate FET having the very thin channel layer, a problem of the variation in the impurity concentration occurs, thus leading to a variation in the threshold voltage.
In order to solve such a problem, there has been proposed a structure for improving the double-gate MOSFET. This structure adopts a system in which the gate electrodes sandwiching a lateral channel being physically separated and electrically insulated from each other, and with a fixed bias voltage being applied to the one gate electrode, the transistor is driven using the other gate electrode, thereby realizing control of the threshold voltage (for example, see Patent Reference 1). FIG. 15A is a plan view showing the MOS structure proposed forth is purpose. FIG. 15B and FIG. 15C are sectional views taken in line A-A′ and line B-B′ in FIG. 15A, respectively. In FIG. 15, like reference numerals refer to like elements in FIG. 14. In FIG. 15, reference numeral 3 denotes a gate electrode; 5 a channel region; 7 a source region; and 8 a drain region. By varying the value of the fixed bias voltage applied to the one gate electrode of the double-gate MOSFET, the threshold voltage of the transistor varies, thereby permitting the threshold voltage to be controlled. However, where the threshold voltage is controlled using the one gate voltage, there is a problem that a driving current necessarily falls. Further, in an actual CMOS circuit, since the mobility of holes in the pMOS is less than that of electrons in the nMOS, in assembling an inverter, current matching based on channel width designing is indispensable. However, the above patent reference does not entirely consider such current driving capability.
In the four-terminal fin type MOSFET structure proposed in Patent Reference 1, since the gate insulating films on both sides of the channel region are simultaneously formed, they have the same thickness. Varying the fixed potential of the one gate electrode surely permits the threshold voltage of the transistor to be controlled, but provides a disadvantage of abruptly increasing the S factor. In order to obviate such a disadvantage, the inventors of this invention have proposed a four-terminal fin type MOSFET having asymmetrical gate insulating films as shown in FIG. 16 (Japanese Patent Appln. No. 2003-40793). FIG. 16A is a plan view showing a device structure thereof. FIG. 16B, 16C are sectional views taken in line A-A′ and line B-B′ in FIG. 16A, respectively. In FIG. 16, like reference numerals refer to like elements in FIG. 15. In FIG. 16, reference numerals 61 and 62 denote gate insulating films having different film thicknesses. In this device structure, by making the thickness of the gate insulating film on the control side larger than the thickness of the gate insulating film on the driving side, the problem of the abrupt increase in the S factor is solved and also the threshold voltage is controlled.
Patent Reference 1
JP-A-2002-270850
Non-Patent Reference 1
D. Hisamoto, et al., “FinFET-A Self-Aligned Double-gate MOSFET Scalable to 20 nm”, IEEE Trans. Electron Devices, Vol. 47, No. 12, 2000, pp. 2320-2325.
Non-Patent Reference 2
Bin YU, et al., “FinFET Scaling to 10 nm Gate Length”, IEDM Tech. Dig., 2002, pp. 251-254.
In the prior art shown in FIG. 14, the occupied area of the device increases, thus reducing the integration degree. Further, in the CMOS inverter having the structure shown in FIG. 14, the channel width of the pMOS can be formed only integer times as large as the channel width of the nMOS so that the current matching could not be done accurately. In addition, since the gate electrodes are coupled with each other, the threshold voltage cannot be controlled using the gate voltage. Further, in also the four-terminal fin type MOSFET shown in FIG. 15 which can control the threshold voltage using the gate electrode and also the four-terminal fin type MOSFET shown in FIG. 16 which can solve the problem of the abrupt increase in the S factor, the multi-fin structure must be adopted for the purpose of the current matching in the CMOS inverter. In these prior arts also, like the first prior art, reduction in the integration degree is problematic.